Design and Performance Evaluation of a Banyan Network Based Interconnection Structure for ATM Switches
In networks capable for transfering high data rates, switches create the most significant bottlenecks. Switches deployed in such fast transmission environments should also operate at very high rates to be able to handle the flood of data arriving at their input ports. If the switches are not properly designed and constructed to handle the high rates of arriving data, then it is not possible to benefit from new networks with high speed transmission media. ATM networks are used to transfer high data rates. In order to design switches appropriate for the ATM environment, various techniques and structures which are mainly based on a high degree of parallelism, self-routing, modularity, and suitability for the VLSI implementation are employed. Among many interconnection structures, banyan networks are widely preferred to be used in multistage ATM switches.
In this thesis, a new banyan network based interconnection structure, called the Plane Interconnected Parallel Network (PIPN), is introduced. The aim is to exploit the properties of banyan networks for use in ATM switches while improving the performance by alleviating drawbacks of banyan networks. It is shown analytically and by simulation that the performance of the PIPN is better than those of banyan network based interconnection structures under heterogeneous traffic requirements. Moreover, all major performance enhancing techniques employed in banyan network based interconnection structures and switches are studied and their taxonomy is presented.
In relation to the proposal of the PIPN and the work to evaluate its performance, a simulation based ATM switch traffic generator which creates traffic adhering to the requirements of ATM networks is also introduced. Furthermore, considering the importance of modeling the heterogeneous traffic, a heterogeneity measure mainly based on the entropy of the incoming switch traffic is proposed.